Philips Research Laboratories
WAY-41, Prof. Holstlaan 4
Eindhoven, The Netherlands
A way to reduce the cost (area) or increase the performance
of asynchronous circuits is to make timing assumptions that
go beyond the isochronic fork. This, however, results in circuits
that are not speed-independent. Such timing assumptions often boil
down to imposing that, of two circuit paths that start at
the same point, one path is faster than the other.
We call speed-dependences of this form chain constraints,
and we handle them as processes in a metric-free formalism.
This paper applies chain constraints to verify single-rail handshake circuits in the context of their timing assumptions, and to evaluate safety margins for delay fluctuations. We discuss the lessons learned, including decomposition and weakening of extended isochronic fork assumptions, (we typically ignore most of the constituent chain constraints) usage of CMOS cell models in the presence of hazards, and correlations between our discrete-state results and analog simulations.
verification, single-rail, handshake circuits, asynchronous circuits, speed-independent circuits, isochronic forks, timing, progress, process spaces
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