An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n x l) static content-addressable memory (CAM) array for cell input stuck-at faults. An input stuck-at fault model for a CAM is defined, and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test's length are proposed.
CMOS CAM, DFT, fault modeling, stuck-at faults, testing.
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