Evaluating Tests for Input Stuck-at Faults in Word-Oriented Static Random-Access Memories

Piotr R. Sidorowicz

Research Report CS-99-05
Department of Computer Science
University of Waterloo
Waterloo, Ontario
Canada N2L 3G1
March, 1999

Abstract

An evaluation of well-known tests: Mats+, Mats++, March Y and March C- with respect to input stuck-at faults in a n-word by l-bit static CMOS random-access memory (SRAM) array is presented. First, an SRAM cell's behavior is analysed at the transistor-network, event-sequence, and finite-state machine (FSM) level. Then, an input stuck-at fault model for an SRAM is defined. We show that the word oriented extensions of the above-mentioned tests detect reliably at most (n+4l)/(2n+4l)*100% of faults in our fault model, which for large n constitutes roughly 50% of faults. We propose a DFT enhancement that would increase this coverage to 100%.

Keywords.

CMOS, design for testability, fault modeling, March C-, March Y, Mats+, Mats++, SRAM, stuck-at faults, testing.

This research was supported by the Natural Sciences and Engineering Research
Council of Canada under grant No. OGP0000871.