Testing for Input Stuck-at Faults in Content-Addressable Memories

P. R. Sidorowicz and J. A. Brzozowski

Research Report CS-98-02
Department of Computer Science
University of Waterloo
Waterloo, Ontario
Canada N2L 3G1
April, 1998

Abstract

Results pertaining to testing for input stuck-at faults in a n-word by l-bit static CMOS content-addressable memory (CAM) array are presented. First, a formal approach to modeling CAM cells is developed. The basis of this approach is the mathematical framework proposed by Brzozowski and Jurgensen for testing and diagnosis of sequential machines. Next, an input stuck-at fault model for a CAM is defined and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Some design-for-testability (DFT) modifications facilitating a further reduction of this test's length are also proposed. Finally, two other CAM tests are verified with respect to our fault model.

Keywords.

CMOS, content-addressable, design for testability, fault modeling, stuck-at faults, testing.

This research was supported by the Natural Sciences and Engineering Research
Council of Canada under grant No. OGP0000871.