Modeling and Testing Transistor Faults in Content-Addressable Memories

P. R. Sidorowicz

Abstract

A behavioral analysis of transistor faults and cell-stuck-at faults in a n-word by l-bit static CMOS CAM array is presented. First, a CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine (FSM) level. Then, a transistor on/open and cell-stuck-at fault model for a CAM is defined. We show that two out of eighteen possible CAM cell's transistor faults cannot be tested reliably by functional tests; however, among faults that are testable, are all those which comprise data-retention faults. We also show that a test, originally designed to detect input stuck-at faults, also detects all reliably testable transistor faults and all cell-stuck-at faults in the model.

Keywords.

CMOS, content-addressable, design for testability, fault modeling, testing, transistor faults.

This research was supported by the Natural Sciences and Engineering Research
Council of Canada under grant No. OGP0000871.