Testing is essential to VLSI circuit production. In the case of memory circuits, the cost of testing often exceeds the cost of manufacture. Current memory testing methods rely on fault models that are inadequate to accurately represent potential defects that occur in modern, often specialized, memories.
We present a formal framework for modeling and testing memories. Simple fault models are created, based on potential circuit-level defects in a given memory. This framework is demonstrated using a content-addressable memory (CAM) as an example. CAMs are used in integrated circuits where searching is a key operation.
A CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine levels. A fault model is defined; it comprises input stuck-at, transistor and bridging faults. We show that functional tests can reliably detect all input stuck-at faults, most transistor faults (including all stuck-open faults), and about 50% of bridging faults. The remaining faults are detectable by parametric tests. A test, of length 7n+2l+9, that detects all the reliably testable faults in an n-word by l-bit CAM was designed. DFT suggestions that reduce the length of this test to 2l+11 are proposed. Two CAM tests, by Giles & Hunter and by Kornachuk et al., are evaluated with respect to the input stuck-at faults. It is shown that the former test fails to detect certain faults; it can be modified to achieve full coverage at the cost of increased length.
To demonstrate the general applicability of our framework, an input
stuck-at fault model of a word-oriented, static random-access memory
(SRAM) is also given. Several commonly known tests are evaluated;
some fail to detect close to 50% of faults in this model.
CAM, CMOS, fault modeling, SRAM, testing.
This research was supported by the Natural Sciences and Engineering Research
Council of Canada under grant No. OGP0000871.